Formal Verification of Digital Circuits at Register Transfer Level using Reachability Analysis

In this paper a fixpoint iteration for reachability analysis of infinite transition systems is presented that can be applied to the verification of circuits at register-transfer level. It is assumed that the system is modeled by using interpreted and uninterpreted functions. To represent infinite sets of states a data structure called symbolic state is introduced. A procedure for deciding the subset-relation of symbolic states is presented. It generalizes known operators and is used to implement the set operators needed in the fixpoint iteration. To avoid non-termination in some cases, the fixpoint iteration is extended by a loop analysis that detects selected versions of counter loops and computes all states reachable by those counters. While other approaches address the reachability analysis of data processing systems or pure counter systems our algorithm can verify circuits containing both arithmetic and counters without manual effort.